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| TSMC Announces 55nm Process Technology Readiness Taiwan Semiconductor Manufacturing Company has unveiled its 55nm process technology, a 90% linear-shrink process from 65nm including I/O and analog circuits. The process delivers significant die cost savings from 65nm, while offering the same speed and 10 to 20% lower power consumption. Because the 55nm process is a direct shrink, IP providers can leverage existing libraries and port their 65nm designs with minimal risk and effort. The 55nm logic family includes general purpose and consumer platforms. Initial production of the 55GP begins this quarter, followed later in the year by 55GC. While TSMC has already engaged many leading customers and IP suppliers on the process, the company will continue to streamline adoption using its CyberShuttle prototyping program that allows multiple customers and IP suppliers to share the costs of a single mask set and prototype wafers on a pilot run. The 55nm CyberShuttle runs are expected to be offered on a bi-monthly basis starting from the beginning of May this year. write your comments about the article :: © 2007 Computing News :: home page |