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| eSilicon Offers Complete 90nm DDR2 Memory Interface Solutions eSilicon is now offering complete, customized Double-Data Rate 2 SDRAM memory interfaces as part of its portfolio of semiconductor development solutions. The optimized 90nm DDR2 memory interface solutions enable data rates in excess of 1 Gbps-per-pin, making them suitable for custom chip developers seeking to implement high-speed interfaces to off-chip memory devices. As speed and complexity requirements for custom chips increase, developers need proven solutions they can trust. DDR2 interfaces are typically one of the most difficult technologies to get right the first time, due to the large number of signals, extremely tight timing and complex architectural design. eSilicon will offer a portfolio of DDR2 interfaces which integrate the company's proven Physical Interface technology with solutions from its wide range of intellectual property partners, enabling end-to-end DDR2 memory interfaces that are optimized for specific applications. The first eSilicon DDR2 interface to be offered targets high-performance computing applications and includes a DDR2 controller from Northwest Logic, DDR2 I/O technology from ARM, and Delay Locked Loop IP from True Circuits, Inc. The eSilicon PHY includes the timing-critical circuitry necessary to meet the precise requirements of a DDR2 SDRAM, including the capture logic, precision write logic, I/O buffers, I/O buffer calibration logic, and multiple settings for termination impedance and output driver impedance. Extensive DFT is included to fully support unit level production test; package design and simulation services are also available. The eSilicon PHY provides a seamless interface to the Northwest Logic DDR2 SDRAM controller, one of the industry's smallest SDRAM solutions. This integration provides high data throughput and clock rates and full programmability of required timing. The controller, in combination with the PHY, provides many additional timing parameters not typically found in other controllers, to further ease integration. ARM Artisan DDR2 I/O technology enables a reliable interface for signal integrity and noise reduction, and the DLL IP from True Circuits, Inc. enables high precision, low jitter clocking of the interface. write your comments about the article :: © 2006 Computing News :: home page |