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| Mentor Processor Support Package for the ARM Cortex-M3 Processor Mentor Graphics has announced the availability of the first Mentor processor support package for the ARM Cortex-M3 processor, which works with Mentor Graphics' Seamless tool to expose hardware/software integration errors inherent in processor-based designs. A Seamless processor support package for the ARM11 MPCore multiprocessor is also available. Mentor's processor support packages for the ARM Cortex-M3 processor and the ARM11 MPCore multiprocessor are based on validated models created by ARM and delivered to Mentor with ARM RealView Electronic System Level (ESL) Application Programming Interfaces (API), a coordinated family of debug, simulation and profiling interfaces that includes the Cycle Accurate Simulation Interface (CASI). These models help reduce design risk by providing a fast, cycle-aware representation that gives design teams a window on silicon performance long before committing to tapeout. Additionally, the virtual processor model provides an excellent level of detail regarding hardware registers, software variables and hardware design issues, enabling simulation runs that closely reflect actual system behavior. Using the high-speed ARM processor models, designers can accurately simulate the entire boot-up process, including device drivers and hardware diagnostics, thereby detecting errors that would prevent boot-up in a hardware prototype. The Seamless hardware/software integration environment provides full control over test execution using the ARM Cortex-M3 processor model, enabling designers to isolate and fix hardware/software interface errors early in the development schedule. To validate that system performance targets are met, Seamless features performance profiling capabilities to accurately measure key design parameters such as bus bandwidth utilization, memory loading, and software profiling, before committing to hardware. The Seamless product is part of Mentor's Scalable Verification platform, a full suite of products that comprises a complete path from HDL simulation to emulation. write your comments about the article :: © 2006 Computing News :: home page |