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| Xilinx Announces PlanAhead 8.1 Xilinx, Inc. has announced immediate availability of the latest version of its PlanAhead software, a hierarchical design and analysis solution that along with Xilinx ISE software delivers a two speed-grade performance advantage for Xilinx Virtex-4 and Spartan-3 FPGAs over competing offerings. The new release also enables significant savings in cost, size and power consumption by simplifying partial reconfiguration for Xilinx FPGAs. Additional PlanAhead 8.1 productivity enhancements include the ExploreAhead feature, which allows designers to employ multiple design strategies to meet their timing goals in the shortest possible time. Optimized Hierarchical Design Delivers Unprecedented Performance Gains Nominated as a finalist in the 2006 DesignVision awards, PlanAhead streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a hierarchical design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options. Recent customer benchmarks yielded average Fmax performance improvements of 30 percent relative to competing FPGAs, which translates to an average of two speed-grade performance and cost advantage for customers. Complex, multi-clock, high-utilization designs yielded improvements of 56 percent on average over competing solutions. Simplified Partial Reconfiguration Reduces Size, Weight, Cost and Power PlanAhead 8.1 software introduces new features and capabilities that streamline the partial reconfiguration design flow. Partial reconfiguration allows customers to save on device count, size, power and cost by allowing predefined portions of an FPGA to be reconfigured while the remainder of the device continues to operate. The new release simplifies the creation of dynamic modules and allows customers to create multiple floorplans for each of their design implementations. Specifically, PlanAhead 8.1 enhancements offer additional design rule checking, overlap detection, automatic macro creation for module-to-module IO, and a new place-and-route wizard. PlanAhead also controls and manages these implementations in ISE in a simple and easy to use design environment. These improvements make partial reconfiguration more accessible for a wider range of applications, including automotive control functions and software defined radio, where it is already being rapidly adopted. Customers interested in partial reconfiguration support in PlanAhead and ISE should contact their local field application engineer. The PlanAhead 8.1 release provides greater levels of automation and a more intuitive graphical interface to dramatically reduce development cycles. The new ExploreAhead feature enables designers and design teams to manage and reuse multiple design strategies while maximizing their computing resources. For example, users can create multiple floorplans, each with its own set of options or strategies and process them in a prioritized manner across multiple processes. This enables customers to achieve their targets in the fastest possible time. Other productivity enhancements include improvements to the schematic viewer for more efficient and intuitive navigation, design analysis and debug and a graphical representation of design hierarchy for enhanced design exploration. write your comments about the article :: © 2006 Computing News :: home page |