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| Inovys Enhances Customers Design Debug Capability Inovys Corporation, a provider of Design For Manufacturing (DFM) solutions for the semiconductor industry, launched Chain Insyte, the latest addition to the Inovys suite of analysis and debug tools for advanced semiconductor devices. The Inovys team will be demonstrating Chain Insyte and other unique data analysis tools in Santa Clara during the International Test Conference (ITC), October 24-26. Chain Insyte enables customers to easily and efficiently isolate and overcome scan chain blockages. This new capability eliminates virtually all of the time spent on debugging scan circuitry and thus removes a significant roadblock in the design debug process and accelerates the time to production. Complex System-On-Chip (SOC) devices continue to increase in circuit density as they decrease in circuit geometries – resulting in a corresponding increase in defect models – necessitating additional on-chip test circuitry. However, in nanometer designs the occurrence of defects in this scan chain test circuitry is increasing disproportionately. Chain Insyte identifies faults in the scan chain in real-time, and more importantly provides the specific location of the fault, using patented algorithms. Previously, customers had to resort to generating custom test patterns to debug these problems - a very manual and time consuming process. In less time than it takes to write the test failure data to disk, Chain Insyte can locate the cause of the problem online, slashing the time for problem resolution from days to minutes. write your comments about the article :: © 2006 Exhibition News :: home page |