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| International Conference on Computer Aided Design The International Conference on Computer Aided Design (ICCAD), the Electronic Design Automation (EDA) industry's top technical conference, is now previewing its "Designers' Perspectives" Technical Track, which will provide for the first time real designers' views and experience on critical topics in electronic design. The track, which will run Tues. Nov. 7 is an integral part of the Conference which will be held November 5-9 at the DoubleTree Hotel in San Jose, California. The first session highlights pressing problems in reliability from designers' perspectives. Marek Patyra from Intel, identifies two fundamental problems with popular methodologies for "Design for Reliability, " and he offers some guidance in reaching reliability constraints. Fabian Klass from P.A. Semi, addresses the use of statistical methods in circuits and outlines some ideas on integrating these methods into CAD tools. Mondira (Mandy) Pant, from Intel, discusses chief challenges in designing a robust and reliable power grid. Noriyuki Ito, of Fujitsu Limited, presents the application of statistical timing analysis to microprocessor design and outlines unsolved related problems. Moderated by Anmol Mathur from Calypto Design Systems, this session focuses on various modeling and validation methodologies to minimize time, efforts, and money required to arrive at verification. Tor Jeremiassen, of TI, highlights the importance of using system modeling environments (ESL based) to validate system-level designs and individual IP blocks in a cohesive environment. Tse-Yu Yeh, from P.A. Semi, will describe the methodology and experience in designing a two-core SOC to support both simulation and emulation for verification. Pascal Urard, STMicroelectronics, discusses the use of verification techniques between system level and RTL. In addition, two Nvidia verification architects, Ira Chayut and David Whipp, focus respectively on the causes of non-determinism and mismatches between C and RTL models, and on grammars to define transaction structures and strategies that ESL designers use to minimize subsequent verification activity. Finally, Jason Stinson, from Intel, describes pre-silicon design and design for test measures that reduce the effort of post-silicon design and verification, including measures for IP blocks. write your comments about the article :: © 2006 Exhibition News :: home page |