DVCon 2007 Announces Call for Paper, Panel and Tutorial Proposals
The 2007 Design and Verification Conference (DVCon), sponsored by Accellera, is now accepting paper, panel and tutorial submissions. Proposals that reflect real experiences using hardware design and verification languages, advanced tools and methodologies are encouraged.
Paper and panel proposals are due September 19, 2006.
DVCon 2007 will be held February 21-23 at the DoubleTree Hotel in San Jose, California. It is the premier conference focusing on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The conference will focus on the use of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++.
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