Icera Collaborates with Magma

Magma Design Automation and Icera announced joint development of Icera's 28-nanometer low-power system-on-chip design flow for its next-generation chipsets. Icera devices are used by OEMs globally to deliver extremely small, fully software-based multimode 4G LTE/3G/2G cellular modems for smartphones, and mobile broadband devices such as USB sticks, tablets and netbooks.

Talus 1.2's new advanced on-chip variation (AOCV) driven optimization significantly reduces pessimistic design margins that are required in traditional flows, and Icera plans to leverage this capability to improve the performance of its soft modem chipsets. Unlike other approaches, this optimization is performed throughout the Talus flow, providing convergent and robust timing while at the same time reducing any area penalty related to OCV effects. With Talus 1.2 designers can improve silicon correlation and minimize power consumption.

Talus 1.2's advanced clock gating techniques help customers significantly reduce both area and power, particularly in the clock network. This allows the core processing functions to achieve required operating frequencies while remaining within a tight power budget.

In addition, Talus 1.2 offers tight timing correlation throughout the flow and timing sign-off through its new MX timing engine derived from Tekton, Magma's standalone static timing analyzer. With reliable timing numbers that Talus delivers early in the design process, designers can make better design decisions throughout the flow and have confidence in achieving timing convergence faster.

write your comments about the article :: 2010 Computing News :: home page