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Cast Expands Its Memory Controller Line

CAST has announced a new IP core that implements a controller for all industry-standard DDR and DDR2 memory devices. The new DDR2-SDRAM-CTRL IP core handles the interaction between SDRAM chips or DIMMs and the processor or a DMA in a system using that memory. The core significantly simplifies memory management challenges for the developer, implementing all the necessary data management, initialization, and address, and burst handling operations.

A high-performance, pipelined and parallel architecture featuring a three-stage processing queue is designed to always get the most out of available system bandwidth. A clever core architecture splits the system interface into separate control, write-data, and read-data paths for easier integration and faster operation. Flexibility is ensured by making all memory parameters runtime-configurable, including timing, memory size, mobile-SDR support, and auto-refresh policies. Power-saving features include power down and self-refresh modes.

Integration of the core is made easier for developers by delivering it with everything needed to for immediate use: one of two different PHY physical device layers and data path queuing elements (FIFOs). The core itself is available in HDL source code, or as an optimized netlist for FPGAs and structured ASICs.

Initial implementations of the core show it to be competitive in performance and area. For example, it achieved 262 MHz with under 1500 LUs in an Altera Sratix II, and 266 MHz with under 1300 slices in a Xilinx Virtex-4. These figures include the FIFOs and other elements not typically offered within a DDR controller core.



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