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AMD and IBM: Using Immersion and Ultra Low-K in 45nm Chips

At the International Electron Device Meeting, IBM and AMD have presented papers describing the use of immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain techniques for application to the 45nm microprocessor process generation. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008. Current process technology uses conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a transparent liquid to fill the space between the projection lens of the step-and-repeat lithography system and the wafer that contains hundreds of microprocessors.

This significant advance in lithography provides increased depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. This immersion technique will give AMD and IBM manufacturing advantages over competitors that are not able to develop a production-class immersion lithography process for the introduction of 45nm microprocessors. For example, the performance of an SRAM cell shows improvements of approximately 15 per cent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, the use of porous, ultra-low-K dielectrics to reduce interconnect capacitance and wiring delay is a critical step in further improving microprocessor performance as well as lowering power dissipation. This advance is enabled through the development of an industry-leading ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 per cent reduction in wiring-related delay as compared to conventional low-K dielectrics.

The continued enhancement of AMD and IBM's transistor strain techniques has enabled the continued scaling of transistor performance while overcoming industry-wide, geometry-related scaling issues associated with migrating to 45nm process technologies. In spite of the increased packing density of the 45nm generation transistors, IBM and AMD have demonstrated an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. This achievement results in the highest CMOS performance reported to date in a 45nm process technology.

IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003. In November 2005, the two companies announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations.



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