contents

hardware
 
PowerQUICC III Processors with QUICC Engine Technology Launched

Broadband access equipment manufacturers now can integrate control and data path functions onto a single semiconductor device with the introduction of an advanced PowerQUICC III processor family from Freescale Semiconductor.

Compatible with previous generation PowerQUICC offerings, Freescale's MPC8568E and MPC8567E processors offer a Gigahertz CPU core, flexible QUICC Engine technology and high-speed system interfaces for multiprotocol interworking. The devices are designed specifically to address increasing performance requirements for broadband access technology and enable the creation of highly advanced equipment including 3G/WiMAX/LTE basestations, RNCs, gateways and ATM/TDM/IP solutions. A high-performance e500 core built on Power Architecture technology works together with 512 KB Level 2 (L2) cache to operate up to 1.33 GHz and deliver more than 3, 000 Dhrystone MIPs.

The processors feature high-speed interfaces including Gigabit Ethernet, PCI Express and Serial RapidIO interconnect technology to enable high-speed links to industry-wide switches, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs) and digital signal processors (DSPs).

The MPC8568E and MPC8567E devices are the first PowerQUICC III processor products to incorporate QUICC Engine technology a programmable system-on-chip (SoC) function block that accelerates communications protocols such as ATM, POS, Ethernet, PPP, HDLC and TDM. QUICC Engine technology enhances overall system performance by offloading multiprotocol processing and interworking from the Power Architecture processing core, which is freed to address higher-level software tasks. It delivers the packet throughput, autonomous multiprotocol interworking, high channel density and software compatibility that equipment manufacturers need to develop advanced yet economical solutions for converged packet networks.

Additional integrated features include a Table Lookup Unit (TLU), a DDR1/2 memory controller, hardware acceleration for double precision floating point and a high-performance security engine. A security engine integrated into both of the devices (as indicated by the E designation) accelerates a wide range of algorithms and modes, such as DES/3DES, AES, ARC-4, Kasumi, MD5, SHA1/2, RSA and Elliptic Curve. It enables the PowerQUICC III processors to offer up to 1 Gbps throughput for widely used commercial security protocols, such as IPSec, SSL/TLS and 3GPP.

Robust enablement support is available to increase reuse, simplify development and speed time to market. The devices ship with standard microcodes, providing industry-proven firmware for existing protocols and downloadable RAM microcode packages that provide support for new functionality or protocols. These microcode offerings help protect existing system investments and enable customization via Freescale's Open QUICC Engine technology developer program.

Freescale also offers a full-featured modular development system (MDS), an AMC form factor reference board for silicon evaluation and a version of its CodeWarrior utility for QUICC Engine technology that accelerates and simplifies initialization and configuration of drivers and communications protocols managed by QUICC Engine technology. Additionally, a wide variety of third-party vendors work in concert with Freescale to offer RTOS support, compilers, debuggers, simulators, reference designs and custom microcode for the MPC8568E and MPC8567E devices.



write your comments about the article :: 2006 Computing News :: home page