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| Synopsys' Validated USB 2.0 nanoPHY IP for TSMC's Nexsys 90-LP Synopsys has announced the immediate availability of the DesignWare USB 2.0 nanoPHY intellectual property (IP) for Taiwan Semiconductor Manufacturing Company's (TSMC's) Nexsys 90-nanometer (nm) low-power (LP) process. The DesignWare USB 2.0 nanoPHY IP is Synopsys' next-generation USB 2.0 mixed-signal PHY targeting low-power and consumer applications. The DesignWare nanoPHY IP for TSMC's 90- nm process was developed with TSMC's proven Nexsys standard cell libraries, which TSMC designed according to their 90-nm design-for-manufacturing rules. This gives system-on-chip (SoC) designers a proven PHY, which lowers risk and enables predictable results. The DesignWare USB 2.0 nanoPHY IP is Hi-Speed USB logo-certified and requires half the power and die area compared to previous-generation solutions. Ideal for applications requiring longer battery life and lower silicon cost, the DesignWare nanoPHY IP will benefit next-generation handheld game machines, feature-rich smart phones, digital cameras and portable audio/video players. A single-port, on-the-go (OTG) configuration takes up only 0.6 square millimeter (mm2) of area and consumes less than 30mA of current during high-speed data transmission. The DesignWare nanoPHY IP is also tunable for optimal yield by enabling adjustments in key PHY performance parameters to address effects related to process variation as well as package- or board-level issues. write your comments about the article :: © 2006 Computing News :: home page |