ST's Innovative Network-on-Chip Technology
STMicroelectronics has announced details of the innovative on-chip interconnect technology that the Company has developed to meet the increasingly demanding needs of current and future SoC designs.
The new technology, called STNoC (ST Network on Chip), builds on ST's existing on-chip communications expertise while adding radical innovation derived from its research in Network-on-Chip (NoC) technologies. The availability of an effective NoC architecture is a crucial factor for cost-effective SoC solutions for next-generation convergence products and, in particular, NoC technology will play a major role in improving design productivity. ST has filed patent applications for an innovative interconnection topology, called Spidergon, which delivers significant cost/performance advantages compared to other NoC topologies.
STNoC addresses one of the most critical issues in SoC technology, which is the interconnection between the many IP blocks that make up the SoC device.
Typically, these include one or more high performance processor cores as well as complex, dedicated IP blocks such as audio/video codecs, a wide range of connectivity IPs (USB, Ethernet, serial ATA, DVB-H, HDMI etc), and memories. Up till now, the interconnection between these blocks has been implemented via traditional circuit-switched buses but it has been widely accepted in recent years that a new interconnection methodology is required to develop SoC devices that contain a billion or more transistors organised in tens or even
hundreds of IP blocks.
Traditional on-chip bus architectures are becoming a bottleneck for two reasons. First, bus architectures need to continually evolve to keep pace with the ever-increasing complexity of SoC devices, which means that the bus interface in each IP block needs to be frequently modified, which increases the time-to-market of new SoC solutions. The second is that rather than behaving like transistors and scaling down in accordance with Moore's law, interconnections in each new technology generation, become more complex as they need to connect more on-chip functions with the result that cost/performance factors such as silicon area, on-chip communications speed and overall power consumption are increasingly dominated by the bus. In the long term, techniques such as optical intra-chip communications, in which ST has already reported world-leading R&D results, may eliminate this problem. In the medium term, new intra-chip interconnection technologies will be required to maintain the combination of price/performance/power improvements required by customers.
Industry experts widely view NoC technology as the solution. Essentially, NoC technology replaces the traditional circuit-switched bus by a packet-based paradigm incorporating a layered protocol stack analogous to a very simplified version of the networking paradigm. In this scenario, proven IP such as processor cores, cache memories, connectivity I/O functions, or specialized IP blocks such as audio/video codecs are simply plucked from a library, added to the SoC design and communicate with each other via a high-speed, low-power, small silicon area, packet-based communications protocol.
In the Spidergon topology, all of the IP blocks are arranged in a ring and each IP block is connected to its clockwise and its counter-clockwise neighbour as in a simple polygonal ring topology. In addition, however, each IP block is also connected directly to its diagonal counterpart in the network, which allows the routing algorithm to minimise the number of nodes that a data packet has to traverse before reaching its destination.
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